Why matching matters
Systematic mismatch in a differential pair causes input-referred offset voltage. In precision op-amps, even a 1 mV offset can be unacceptable. Layout is your primary tool for minimising it.
Common-centroid placement
Split each transistor into two halves (A1, A2 and B1, B2) and arrange them as A1–B1–B2–A2 along a row. Gradients in oxide thickness or doping now affect both devices equally, cancelling first-order errors.
Interdigitation
For matched resistors or capacitors, interdigitate the fingers: R1–R2–R1–R2. Add dummy cells at both ends to equalise etch loading. The VirtuChip.AI layout kit includes parameterised pcells for matched pairs with automatic dummy insertion.
Guard rings
Surround sensitive nodes with n-well or p-substrate guard rings tied to the appropriate supply. This blocks lateral bipolar injection and reduces substrate noise coupling.