What is a PLL?
A phase-locked loop is a feedback system that locks the phase of a voltage-controlled oscillator (VCO) to a reference signal. They appear in clock generation, frequency synthesis, and clock-data recovery.
Key blocks
- Phase-frequency detector (PFD) — compares reference and divided VCO phases.
- Charge pump — converts PFD pulses to a current that charges the loop filter.
- Loop filter — a low-pass RC network that sets bandwidth and phase margin.
- VCO — oscillates at a frequency proportional to its control voltage.
- Divider (÷N) — divides the VCO output so the PFD sees the same frequency as the reference.
Loop filter design
For a type-II, second-order PLL the open-loop transfer function is:
L(s) = Kpd · Kvco/N · Z(s) / swhere Z(s) is the loop filter impedance. Place the zero at ≈ 1/10 of the reference
frequency for good phase margin (≥ 50°). The VirtuChip.AI PLL package includes a MATLAB script
that calculates R and C values given your target bandwidth and VCO gain.
Simulating lock time in SPICE
Load the provided pll_tb.scs testbench into Spectre. The transient simulation starts with the VCO free-running; watch the control voltage settle to verify lock time meets spec. Typical lock time for a 2.4 GHz PLL is 5–20 µs.